document no. 70-0144-04 www.psemi.com page 1 of 8 ?2010-2011 peregrine semiconductor corp. all rights reserved. figure 2. package type 20-lead 4 x 4 mm qfn product specification 75 ? spdt catv ultracmos? switch 5 mhz - 3 ghz product description figure 1. functional diagram pe4256 features ?? 75 ? characteristic impedance ?? integrated 75 ? terminations ?? ctb performance of -90 dbc ?? high isolation 65 db at 1000 mhz ?? low insertion loss: typically 0.5 db at 5 mhz, 0.9 db at 1000 mhz ?? high input ip3: >50 dbm ?? cmos two-pin control ?? single +3 volt supply operation ?? low current consumption: 8 a ?? unique all off terminated mode ?? 4 x 4 mm qfn package parameter condition minimum typical maximum units operating frequency 1 5 3000 mhz insertion loss 5-250 mhz 250-750 mhz 750-1000 mhz 1000-2200 mhz 0.5 0.8 0.9 1.1 0.6 0.95 1.1 1.3 db isolation 5-250 mhz 250-750 mhz 750-1000 mhz 1000-2200 mhz 75 65 62 49 80 70 65 52 db input ip2 2 5-1000 mhz 80 dbm input ip3 2 5-1000 mhz 50 55 dbm input 1db compression 2 1000 mhz 29 31 dbm ctb / cso 77 & 110 channels; power out = 44 dbm v -90 dbc switching time 50% ctrl to 10/90% rf 2 s video feedthrough 3 5-1000 mhz 15 mv pp notes: 1. device linearity will begin to degrade below 5 mhz. 2. measured in a 50 ? system. 3. measured with a 1 ns risetime, 0/3 v pulse and 500 mhz bandwidth peregrine specification 71-0013-01 the pe4256 is an ultracmos? switch designed for catv applications, covering a broad frequency range from 5 mhz up to 3 ghz. this single-supply spdt switch integrates a two-pin cmos control interface. it also provides low insertion loss with extremely low bias requirements while operating on a single 3- volt supply. in a typical catv application, the pe4256 provides for a cost effective and manufacturable solution when compared to mechanical relays. the pe4256 is manufactured on peregrine?s ultracmos? process, a patented variation of silicon-on-insulator (soi) technology on a sapphire substrate, offering the performance of gaas with the economy and integration of conventional cmos. table 1. electrical specifications @ +25 c, v dd = +3 v (z s = z l = 75 ? ) logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe4256 page 2 of 8 ?2010-2011 peregrine semiconductor corp. all rights reserved. document no. 70-0144-04 ultracmos? rfic solutions table 2. pin descriptions table 3. absolute maximum ratings electrostatic discharge (esd) precautions when handling this ultracmos? device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the rating specified. table 4. dc electrical specifications @ 25 c figure 3. pin configuration (top view) no. name description 1 gnd ground 2 gnd ground 3 1 rf1 rf i/o 4 4 gnd ground 5 gnd ground 6 gnd ground 7 4 gnd ground 8 1 rfc common 9 4 gnd ground 10 gnd ground 11 gnd ground 12 4 gnd ground 13 1 rf2 rf i/o 14 gnd ground 15 gnd ground 16 2 c2 control 2 17 2 c1 control 1 18 3 vss/gnd negative supply option 19 gnd ground 20 vdd supply paddle gnd exposed ground paddle notes: 1. rf pins 3, 8, and 13 must be at 0 vdc. the rf pins do not require dc blocking capacitors for proper operat ion if the 0 vdc requirement is met. 2. pins 16 and 17 are the cmos c ontrols that set the three operating states. 3. connect pin 18 to gnd to enable the on-chip negative voltage generator. connect pin 18 to v ss (-3 v) to bypass and disable internal - 3 v supply generator. 4. customer can add external resist ance to ground to change or modify termination resistance. symbol parameter/condition min max unit v dd power supply voltage -0.3 4.0 v v i voltage on ctrl input -0.3 v dd + 0.3 v p rf rf cw power 24 dbm t st storage temperature -65 150 c t op operating temperature -40 85 c v esd esd voltage (human body model) 1000 v parameter min typ max unit v dd power supply 2.7 3.0 3.3 v i dd power supply current (v dd = 3 v, v cntl = 3 v) 8 20 a control voltage high 70% v dd v control voltage low 30% v dd v moisture sensitivity level the moisture sensitivity level rating for the pe4256 in the 20-lead 4 x 4 mm qfn package is msl1. exceeding absolute maximum ratings may cause permanent damage. operation should be restricted to the limits in the operating ranges table. operation between operating range maximum and absolute maximum for extended periods may reduce reliability. logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe4256 page 3 of 8 document no. 70-0144-04 www.psemi.com ?2010-2011 peregrine semiconductor corp. all rights reserved. table 5. rf path truth table table 6. termination truth table notes: 1. the operation of the pe4256 is not supported or characterized in the c1 = v dd and c2 = v dd state. 2. "x" denotes termination enabled. c1 c2 rfc ? rf1 rfc ? rf2 low low off off low high off on high low on off high high n/a 1 n/a 1 c1 c2 rfc ? 75 ? rf1 ? 75 ? rf2 ? 75 ? low low x 2 x 2 x 2 low high x 2 high low x 2 high high n/a 1 n/a 1 n/a 1 switching frequency the pe4256 has a maximum 25 khz switching rate when the internal negative voltage generator is used (pin 18 = gnd). latch-up avoidance unlike conventional cmos devices, ultracmos? devices are immune to latch-up. logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe4256 page 4 of 8 ?2010-2011 peregrine semiconductor corp. all rights reserved. document no. 70-0144-04 ultracmos? rfic solutions evaluation kit the spdt switch evaluation kit was designed to ease customer evaluation of the pe4256 spdt switch. the rf common port (rfc) is connected through a 75 ? transmission line to j2. port 1 and port 2 are connected through 75 ? transmission lines to j1 and j3. a through transmission line connects f connectors j4 and j5. this transmission line can be used to estimate the loss of the pcb over the environmental conditions being evaluated. the board is constructed with four metal layers in fr4 material with a total thickness of 0.062". the transmission lines were designed using a coplanar waveguide with ground plane (28 mil core, 21 mil width, 30 mil gap). j6 provides a means for controlling dc and digital inputs to the device. the provided jumpers short the package pin to ground for logic low. when the jumper is removed, the pin is pulled up to v dd for logic high. when the jumper is in place, 3 a of current will flow through the 1 m ? pull-up resistor. this extra current should not be attributed to the device. proper pcb design is essential for full isolation performance. this evaluation board demonstrates good trace and ground management for minimum coupling and radiation. figure 4. evaluation board layouts figure 5. evaluation board schematic peregrine specification 102/0195~02a peregrine specification 101/0148~03a logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe4256 page 5 of 8 document no. 70-0144-04 www.psemi.com ?2010-2011 peregrine semiconductor corp. all rights reserved. -100 -90 -80 -70 -60 -50 -40 0 500 1000 1500 2000 2500 3000 rf1 - rf2 (rf1 thru) rf1 - rf2 (rf2 thru) rf1 - rf2 (rf1 & 2 open) isolation (db) frequency (mhz) -100 -90 -80 -70 -60 -50 -40 0 500 1000 1500 2000 2500 3000 rfc - rf1 (rf2 open) rfc - rf2 (rf1 open) isolation (db) frequency (mhz) -100 -90 -80 -70 -60 -50 -40 0 500 1000 1500 2000 2500 3000 rfc - rf1 (rf2 closed) rfc - rf2 (rf1 closed) isolation (db) frequency (mhz) -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 500 1000 1500 2000 2500 3000 25c -40c 85c insertion loss (db) frequency (mhz) typical performance data from -40 c to +85 c, 75 ? impedance figure 7. input to output isolation (closed) figure 9. isolation ? rf1 to rf2 figure 8. input to output isolation (open) figure 6. insertion loss (rfc to rf1 or rf2) logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe4256 page 6 of 8 ?2010-2011 peregrine semiconductor corp. all rights reserved. document no. 70-0144-04 ultracmos? rfic solutions -35 -30 -25 -20 -15 -10 -5 0 0 500 1000 1500 2000 2500 3000 rfc terminated rfc - rf1 closed return loss (db) frequency (mhz) typical performance data @ +25 c, 75 ? impedance (unless otherwise noted) figure 11. rf1 return loss figure 13. linearity (50 ? system impedance) figure 12. rf2 return loss figure 10. rfc return loss 0 10 20 30 40 50 60 0 500 1000 1500 2000 2500 3000 input ip3 1db compression power (dbm) frequency (mhz) logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe4256 page 7 of 8 document no. 70-0144-04 www.psemi.com ?2010-2011 peregrine semiconductor corp. all rights reserved. 20-lead 4 x 4 mm qfn figure 14. package drawing (mm) 4280 yyww zzzzz yyww = date code zzzzz = last five digits of psc lot number figure 15. marking specifications logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe4256 page 8 of 8 ?2010-2011 peregrine semiconductor corp. all rights reserved. document no. 70-0144-04 ultracmos? rfic solutions advance information : the product is in a formative or design stage. the datasheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification: the datasheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification: the datasheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify customers of the intended changes by issuing a cnf (customer notification form). the information in this datasheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, and utsi are registered trademarks and ultracmos, harp, multiswitch and dune are trademarks of peregrine semiconductor corp. sales contact and information for sales and contact information please visit www.psemi.com. table 7. ordering information order code part mark ing description package shipping method 4256-00 pe4256-ek pe4256-20qfn 4 x 4 mm-ek evaluation kit 1 / box PE4256MLIAA 4256 pe4256-20qfn 4 x 4 mm-75 green 20-lead 4 x 4 mm qfn, nipdau lead finish 75 units / tube PE4256MLIAA-z 4256 pe4256-20qfn 4 x 4 mm-3000 green 20-l ead 4 x 4 mm qfn, nipdau lead finish 3000 units / t&r ek4256-01 pe4256-ek pe4256-20qfn 4 x 4 mm-ek evaluation kit 1 / box 4256-52 4256 pe4256g-20qfn 4 x 4 mm-3000c green 20-lead 4 x 4 mm qfn, matte tin lead finish 3000 units / t&r figure 15. tape and reel drawing logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
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